The present invention relates to a multi-clock controller, and more particularly relates to a multi-clock controller which has the capability to power down and power up the clock signals used for chips used in lower power applications, using either one of at least two different clock signals.
In integrated circuit applications, such as in low power computers (i.e. notebook or laptop), there is a need for system clocks to be turned off and on in an orderly fashion, with no runt pulses or metastable conditions. Turning the clocks off at appropriate times will greatly reduce the power consumption and will extend the battery life of the system.
A second need in such systems is the capability for automatic selection of multiple clock sources. Such a capability enables the switching of clock inputs to a chip containing the circuit from different sources without any intervention being necessary by the user. Such a capability would save on the number of external pins required and would make the circuit operation more transparent to the user.